Design closure of current chip designs has become complex. The ability to estimate how long and how much resources will be consumed closing the design of a large circuit has become unpredictable in the early phase of the design closure. Design closure runs of the large circuits are taking a long time. Margins are being used to handle risks of not being able to close timing. Constraints are either being merged or used in multiple modes. Furthermore, the projects are not always staffed correctly. As a result, scheduling remains unpredictable and the circuits are often delivered late.
To account for the unpredictability, many projects add margins or over-constraining the design in early phases. Some projects use multiple runs and multiple loops to reach design closure. More licenses and machines have been used to permit parallel operations. Hiring more engineers sometimes helps achieve design closure in a reasonable amount of time. Statistical static timing analysis is also used in the industry to verify the timing of a design, which might include the statistical handling of clock trees and ramp-up times.
Unfortunately, the existing solutions can have drawbacks. Adding the margins and/or over-constraining the designs are based on rules of thumb or past experience that is not always available. Having more engineers assigned to the projects does not always result in a faster turn around time. Furthermore, conducting several design closure runs on the same chip in parallel using several machines is inefficient. Therefore, a resource efficient method is desired for design closure projects.